 | |  | |  | |  | |  |
novel platform-based, communication-centric
ESL synthesis flow synthesis flow that
automatically generates high-quality RTL
code from behavior-level and system-level
SystemC/C descriptions for design and
implementation of application-specific
integrated circuits (ASICs), Structured ASICs,
and field-programmable gate arrays (FPGAs).
- © 2006 AutoESL Design Technologies, Inc.
