AutoPilot™ FPGA Altera
AutoPilot™ FPGA Altera is AutoESL’s high level synthesis tool for Altera FPGAs. AutoPilot™ FPGA Altera takes a complex algorithm in the form of C, C++ or SystemC description or a combination of these languages and automatically generates an equivalent RTL that is ready for synthesis into a Altera device.
The benefits of AutoPilot™ FPGA Altera are:
- Multi-language support and the broadest language coverage in the industry. Customers can run synthesis on their code with minimal changes to it.
- Fast time to QoR that is equal to or better than hand-coded RTL.
- Support for multiple application domains
- Architecture aware synthesis that delivers the best possible QoR
- Automatic use of Altera on-chip memories and DSP elements
- Automatic use of Altera floating point library
- Supports usage of Altera IP cores such as Avalon bus components
- Comprehensive Device Support
- Stratix IV, Stratix III, Stratix II, Stratix, Cyclone III
- Automatically generates all files required for FPGA implementation using Altera Quartus II, SOPC Builder, and Synplify tools
- Simulation and debugging flow works with ModelSim and Aldec simulators
