Products

AutoESL’s high level synthesis is targeted for ASIC and FPGA design.

AutoPilot™ ASIC

AutoPilot™ ASIC is AutoESL’s high level synthesis tool for ASICs. It understands and utilizes the target technology intelligently to generate RTL that produces the best possible QoR for the architecture that is being targeted. It will generate RTL that is optimized to meet design goals along the throughput-power-area-timing axis. AutoPilot™ ASIC will reduce the verification time by orders of magnitude due the advantage of working at a higher level of abstraction in C, C++ or SystemC. Learn more >>

AutoPilot™ FPGA

AutoPilot™ FPGA is AutoESL’s architecture aware synthesis tool for FPGAs. Based on the FPGA device that is being targeted, the tool intelligently uses all of the functions, memories and cores available in the device, thereby generating RTL that is equal to or better than hand-coded RTL in only a fraction of the time it takes to develop RTL manually. It is fast and easy to use, enabling designers to get to the best possible QoR (Quality of Results) on their design very quickly. Learn more >>

AutoPilot™ FPGA Xilinx

AutoPilot™ FPGA is AutoESL’s architecture aware synthesis tool for Xilinx FPGAs. Based on the Xilinx FPGA device that is being targeted, the tool intelligently uses all of the functions, memories and cores available in the device, thereby generating RTL that is equal to or better than hand-coded RTL in only a fraction of the time it takes to develop RTL manually. It is fast and easy to use, enabling designers to get to the best possible QoR (Quality of Results) on their design very quickly. AutoPilot is well integrated into the Xilinx flow. Learn more >>

AutoPilot™ FPGA Altera

AutoPilot™ FPGA is AutoESL’s architecture aware synthesis tool for Altera FPGAs. Based on the Altera FPGA device that is being targeted, the tool intelligently uses all of the functions, memories and cores available in the device, thereby generating RTL that is equal to or better than hand-coded RTL in only a fraction of the time it takes to develop RTL manually. It is fast and easy to use, enabling designers to get to the best possible QoR (Quality of Results) on their design very quickly. AutoPilot is well integrated into the Altera flow. Learn more >>