About AutoESL

AutoESL is the leading provider of high level synthesis for FPGAs and ASICs. AutoESL was founded in 2006 based on advanced proprietary technology that was nurtured, developed, and exclusively licensed from UCLA. AutoESL has now deployed this solution at many leading edge system and semiconductor companies.

The Era of ESL is Finally Dawning

Why, for over a decade, have all previous attempts at High Level Synthesis (HLS) failed - and continue to fail?

1. IP re-use provided enough productivity until now?
2. No appreciation of differences between FPGA and ASIC HLS?
3. Selective language support - HLS tools unable to truly support C, C++, SystemC, etc.?
4. Limited language constructs in the 'supported' language causing massive re-coding?
5. Quality of RTL generated?
6. RTL optimized for a single axis - area or performance?
7. Power optimization not even considered?
8. All of the above

 

The answer, of course, is h) All of the above.

All of the current HLS tools are limited by the era in which they were developed and are unable to truly solve all the above problems. In fact, it is difficult to tell the difference between the various vendors other than they are arguing over which language ought to be supported.

The Age of HLS is finally dawning... enabled by the right technology from AutoESL!

AutoESL is now deploying a HLS solution that truly realizes the promise of ESL by solving all the above problems, in a manner that can be deployed well beyond a few specialists.